;LZ4GV 2021- Firmware EQU .2 list p=16f18446 ; list directive to define processor #include ; processor specific variable definitions ;Set Configuration Register __CONFIG _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_OFF & _FCMEN_OFF ; _FEXTOSC_LP _RSTOSC_HFINT1 _CLKOUTEN_ON _CSWEN_ON _FCMEN_ON ;_RSTOSC_HFINT32 EQU H'3F8F'; HFINTOSC with OSCFRQ= 32 MHz and CDIV = 1:1 ;_RSTOSC_HFINTPLL EQU H'3F9F'; HFINTOSC with 2x PLL, with OSCFRQ = 16 MHz and CDIV = 1:1 (FOSC = 32 MHz) ;_RSTOSC_EXT4X EQU H'3FAF'; EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits ;_RSTOSC_SOSC EQU H'3FCF'; SOSC ;_RSTOSC_LFINT EQU H'3FDF'; LFINTOSC ;_RSTOSC_HFINT1 EQU H'3FEF'; HFINTOSC (1MHz) ;_RSTOSC_EXT1X EQU H'3FFF'; EXTOSC operating per FEXTOSC bits ;_FEXTOSC_OFF ;Oscillator not enabled ;_FEXTOSC_LP ;LP (crystal oscillator) optimized for 32.768kHz; PFM set to low power ;_FEXTOSC_XT ;XT (crystal oscillator) above 500kHz, below 4MHz; PFM set to medium power ;_FEXTOSC_HS ;HS (crystal oscillator) above 4MHz; PFM set to high power ;_FEXTOSC_ECL ;ECL below 500kHz; PFM set to low power ;_FEXTOSC_ECM ;ECM for 500kHz to 8MHz; PFM set to medium power ;_FEXTOSC_ECH ;ECH above 8MHz; PFM set to high power __CONFIG _CONFIG2, _MCLRE_OFF & _PWRTS_PWRT_64 & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _ZCDDIS_OFF & _PPS1WAY_OFF & _STVREN_OFF ;_BORV_HI = 2.70V ; _MCLRE_ON _PWRTS_PWRT_16 _LPBOREN_ON _BOREN_OFF _BORV_HI _ZCD_ON _ZCDDIS_ON _PPS1WAY_ON _STVREN_ON ;_BORV_LO = 2.45V ; _PWRTS_PWRT_1 _BOREN_SBOREN _WRT_HALF ; _PWRTS_OFF _BOREN_NSLEEP _WRT_ALL __CONFIG _CONFIG3, _WDTCPS_WDTCPS_0 & _WDTE_OFF & _WDTCPS_WDTCPS_31 & _WDTCCS_SC ; _WDTE_ON _WDTCWS_WDTCWS_0 _WDTCCS_SOSC ; _WDTE_SWDTEN _WDTCWS_WDTCWS_1 _WDTCCS_HFINTOSC ; _WDTE_NSLEEP _WDTCWS_WDTCWS_2 _WDTCCS_LFINTOSC __CONFIG _CONFIG4, _BBSIZE_BB8K & _BBEN_OFF & _SAFEN_OFF & _WRTAPP_OFF & _WRTB_OFF & _WRTC_OFF & _WRTD_OFF & _WRTSAF_OFF & _LVP_OFF ; _BBSIZE_BB64K _BBEN_ON _SAFEN_ON _WRTAPP_ON _WRTB_ON _WRTC_ON _WRTD_ON _WRTSAF_ON _LVP_ON __CONFIG _CONFIG5, _CP_OFF ; _CP_ON OSCTUNE_MNL EQU .0 ;Central frequency min .32 - .63 0 .1 - .31 max ; #define PORTA0 PORTA,0 ;Pin_19 #define PORTA1 PORTA,1 ;Pin_18 #define PORTA2 PORTA,2 ;Pin_17 #define PORTA3 PORTA,3 ;Pin_4 #define PORTA4 PORTA,4 ;Pin_3 #define PORTA5 PORTA,5 ;Pin_2 #define PORTA5_IO TRISA,5 ; #define PORTB4 PORTB,4 ;Pin_13 #define PORTB5 PORTB,5 ;Pin_12 #define PORTB6 PORTB,6 ;Pin_11 #define PORTB7 PORTB,7 ;Pin_10 #define PORTB7_IO TRISB,7 ; #define PORTC0 PORTC,0 ;Pin_16 #define PORTC1 PORTC,1 ;Pin_15 #define PORTC2 PORTC,2 ;Pin_14 #define PORTC3 PORTC,3 ;Pin_7 #define PORTC4 PORTC,4 ;Pin_6 #define PORTC5 PORTC,5 ;Pin_5 #define PORTC6 PORTC,6 ;Pin_8 #define PORTC7 PORTC,7 ;Pin_9 #define PORTC7_IO TRISC,7 ; ;0x20 to 0x6F Bank 0 #define STATBIT 0x20,0 ; ;TMR0MEM EQU 0x6A ; ;TMR1LMEM EQU 0x6B ; ;TMR1HMEM EQU 0x6C ; ;FSRMEM EQU 0x6D ; ;PCLMEM EQU 0x6E ; ;0x70 to 0x7F Bank 0,1,2,3..... ACQT EQU 0x79 ;ADC Bank1 RADRESL EQU 0x7A ;ADC RADRESH EQU 0x7B ;ADC REEADR EQU 0x7C ;EEPROM REEDATA EQU 0x7D ;EEPROM OPTIONMEM EQU 0x7E ; #define GIEМЕМ 0x7F,0 ; ;0x0A0 to 0x0EF Bank 1 ;0x120 to 0x16F Bank 2 ;0x1A0 to 0x1EF Bank 3 ;0x220 to 0x26F Bank 4 ;0x2A0 to 0x2EF Bank 5 ;0x320 to 0x32F Bank 6 #define WPAGE PCLATH,3 ;0- Work. Page0 1- Work. Page1 #define Bank0_1 BSR,0 ;0= Bank0 1= Bank1 INDF EQU INDF0 FSR EQU FSR0L ORG 0xF000 ;Initialize EEPROM locations 0xF000 - 0xF0FF DE 0x00,0x01,0x02,0x03 ORG 0x0000 GOTO START ;**************************************************************** ORG 0x0004 ;Interrupt vector location clrf BSR ;Bank0 clrf PCLATH ;0- Work. Page0 movlb .14 btfsc PIR0,IOCIF ;PORTA/PORTB Change Interrupt Global Flag GOTO INT_PORTCHANGE ;--> btfsc PIR0,INTF ;INT External Interrupt Flag GOTO INT_EXTINT btfsc PIR0,TMR0IF ;Overflow TMR0 GOTO INT_TMR0 ;--> btfsc PIR4,TMR1IF ;Overflow TMR1 GOTO INT_TMR1 ;--> movlb .0 GOTO INT_END ;--> ;------------------------------------------------------------------------------ ; USER INTERRUPT SERVICE ROUTINE GOES HERE ;------------------------------------------------------------------------------ INT_PORTCHANGE MOVLB .62 ;Bank7 CLRF IOCAF ;PORTA Flag Register Interrupt-On-Change CLRF IOCBF ;PORTB Flag Register Interrupt-On-Change movlb .14 bcf PIR0,IOCIF ;PORTA/PORTB Change Interrupt Global Flag movlb .0 GOTO INT_END ;--> ; INT_EXTINT movlb .0 ;.... movlb .14 ;Bank14 bcf PIR0,INTF ;INT External Interrupt Flag movlb .0 GOTO INT_END ;--> ; INT_TMR0 movlb .0 ;.... movlb .14 ;Bank14 BCF PIR0,TMR0IF ;Overflow TMR0 movlb .0 GOTO INT_END ;--> ; INT_TMR1 movlb .0 ;.... movlb .14 ;Bank14 bcf PIR4,TMR1IF ;TMR1 Overflow Interrupt Flag movlb .0 GOTO INT_END ;--> ; INT_END ;Automatically handles context restoration for W, STATUS, BSR, FSR, and PCLATH RETFIE ;Return From Interrupt / Enable Global Interrupts ;**************************************************************** BEGIN MOVLW 0x20 ;Start Address RAM. MOVWF FSR0L ; CLRF FSR0H CLRF FSR1L CLRF FSR1H CLRRAM ; CLRF INDF0 ; ; INDF1 ; MOVLW 0x7F ;End Address RAM. SUBWF FSR0L,W ;FSR0H INCF FSR0L,F ; BTFSS STATUS,C ;FSR = or > W C=1 GOTO CLRRAM ;FSR < W C=0 ;********** Начало *********** MAIN ;------------------------------------------------------------------------------ ; MAIN PROGRAM movlb .11 clrf TMR0L ; clrf TMR0H ; movlb .14 ;Bank14 bcf PIR0,TMR0IF ;Overflow TMR0 movlb .0 ; movlb .4 clrf TMR1L clrf TMR1H MOVLW 0xDB ; MOVWF TMR1L ; MOVLW 0x0B ; MOVWF TMR1H ; BCF PIR1,TMR1IF ;Overflow TMR1 ; MOVLW .100 ; ; SUBWF RADRESH,W ;ADRESH > W C=1 ; BTFSC STATUS,C ;ADRESH = W C=1 ; GOTO ;ADRESH < W C=0 ; GOTO ; ; movlw .50 ; sublw .20 ;W < .20 C=1 ; BTFSC STATUS,C ;W = .20 C=1 ; GOTO ;W > .20 C=0 ; GOTO ; MOVLB .1 ;Bank 1 ;MOVF OPTION_REG,W ;Запомня състоянието на OPTION_REG. ;MOVWF OPTIONMEM ;Променя TMR0 ANDLW B'11111000' ;Нулира само PS2 PS1 PS0 IORLW B'00000001' ;Променя Fosc/4/4 = 4uS ;MOVWF OPTION_REG ; MOVLB .0 ;Bank 0 MOVLB .1 ;Bank 1 MOVF OPTIONMEM,W ; ;MOVWF OPTION_REG ; MOVLB .0 ;Bank 0 ;CALL READE ;In:F(REEADR) Out:F(REEDAT),W ;CALL WRITE ;In:F(REEADR,REEDATA) ;MOVLW RA0_AN0 ; ;CALL READ_ADC ;In: W(Analog Select) Out:F(RADRESH,RADRESL) ; MOVLW 0xFF ;Clearing Interrupt Flags XORWF IOCAF, W ANDWF IOCAF, F ; MOVLB .2 ;Bank2 ;BTFSS CM1CON0,C1OUT ; ;NOP ;BTFSS CM2CON0,C2OUT ; ;NOP MOVLB .0 ;Bank0 ;******* BCF INTCON,GIE ;Disable All INTs. BTFSC INTCON,GIE ;See AN576 GOTO $-2 ; BSF INTCON,GIE ;Enable All INTs. ;******* GOTO MAIN ; #define SS1_Pin PORTC,6 ;Pin_8 movlw 0x00 ;MSB iorlw b'10000000' ;Next byte Write bit=1 bcf SS1_Pin ;PORT Pin Enable Chip Select Output (low) CALL MASTER_SPI1 movlw 0x00 ;LSB Write CALL MASTER_SPI1 bsf SS1_Pin ;Disable Chip Select Output (high) movlw 0x00 ;7bit andlw b'01111111' ;Next byte Read bit7=0 bcf SS1_Pin ;PORT Pin Enable Chip Select Output (low) CALL MASTER_SPI1 CALL MASTER_SPI1 ;8bit Read Out:W bsf SS1_Pin ;Disable Chip Select Output (high) ;movwf ;********************************************************************** MASTER_SPI1 ;In: W Out:W movlb .4 movwf SSP1BUF ;Synchronous Serial Port Receive Buffer/Transmit Register MASTER_SPI1a btfss SSP1STAT,BF ;1= Receive complete, SSP1BUF is full 0= Receive not complete, SSP1BUF is empty Read Only goto MASTER_SPI1a movf SSP1BUF,W ;Get Data from SSPBUF 0 -> SSP1STAT,BF ;btfsc SSP1CON1,WCOL ;Write Collision Detect bit Clear by Software ;btfsc SSP1CON1,SSPOV ;Receive Overflow Indicator bit Clear by Software movlb .0 RETURN ;********************************************************************** MOVLW '$' CALL UAT ;********************************************************************** UAT ;Universal Asynchronous Transmiter In: W ;BTFSS PIR1,TXIF GOTO $-1 MOVLB .3 ;Bank3 MOVWF TXREG MOVLB .0 ;BTFSS PIR1,TXIF ;1= Transmit Buffer is Empty GOTO $-1 ;;XORWF CHSUM,F ;Пресмята контролната сума на изпратените данни. RETURN ;********************************************************************** ;------------------------------------------------------------------------------ ;********** Край ************* ;********************************************************************** WRITE ;In:F(REEADR,REEDATA) MOVLB .16 MOVF REEADR,W ; MOVWF NVMADRL movlw 0x70 ;0x70XX -EEPROM Address movwf NVMADRH ;6:0 MOVF REEDATA,W MOVWF NVMDATL clrf NVMDATH ;5:0 ;BCF NVMCON1,FREE ;0= The next WR command writes without erasing. ;BCF NVMCON1,LWLO ;Load Write Latches Only bit BSF NVMCON1,NVMREGS ;1= Access EEPROM, DIA, DCI, Configuration, User ID and Device ID Registers 0= Access Program Flash Memory BCF GIEМЕМ ; BTFSC INTCON,GIE ;Запазва състоянието. BSF GIEМЕМ ; BCF INTCON,GIE ;Disable INTs. BTFSC INTCON,GIE ;See AN576 GOTO $-2 ; BSF NVMCON1,WREN ;1= Allows program/erase cycles MOVLW 0x55 ; MOVWF NVMCON2 ; MOVLW 0xAA ; MOVWF NVMCON2 ; BSF NVMCON1,WR ; BTFSC NVMCON1,WR ;1= Write Cycles 0= Write cycles to the EEPROM is complete GOTO $-1 ;-^ ;btfss NVMCON1,WRERR ;0= All write operations have completed normally. ;NOP BCF NVMCON1,WREN ;disable write BTFSC GIEМЕМ ; BSF INTCON,GIE ; movlb .0 ;Bank0 RETURN ; READE ;In:F(REEADR) Out:F(REEDAT),W MOVLB .16 ;Bank3 MOVF REEADR,W MOVWF NVMADRL movlw 0x70 ;0x70XX -EEPROM Address movwf NVMADRH ;6:0 BSF NVMCON1,NVMREGS ;1= Access EEPROM BSF NVMCON1,RD ;1 - initiates an EEPOM read BTFSC NVMCON1,RD ;rd done? GOTO $-1 ;no then loop MOVF NVMDATL,W MOVWF REEDATA MOVLB .0 ;Bank0 RETURN ; ; ;Analog Select ; EQU B'00111111' ;Fixed Voltage Reference (FVR) 2 ; EQU B'00111110' ;Fixed Voltage Reference (FVR) 1 ; EQU B'00111101' ;DAC1 output ; EQU B'00111100' ;Temperature Indicator ; EQU B'00111011' ;AVSS (Analog Ground) RC7_AN16 EQU B'00010111' ;RC7/ANC7 RC6_AN15 EQU B'00010110' ;RC6/ANC6 RC5_AN14 EQU B'00010101' ;RC5/ANC5 RC4_AN13 EQU B'00010100' ;RC4/ANC4 RC3_AN12 EQU B'00010011' ;RC3/ANC3 RC2_AN11 EQU B'00010010' ;RC2/ANC2 RC1_AN10 EQU B'00010001' ;RC1/ANC1 RC0_AN9 EQU B'00010000' ;RC0/ANC0 RB7_AN8 EQU B'00001111' ;RB7/ANB7 RB6_AN7 EQU B'00001110' ;RB6/ANB6 RB5_AN6 EQU B'00001101' ;RB5/ANB5 RB4_AN5 EQU B'00001100' ;RB4/ANB4 RA5_AN4 EQU B'00000101' ;RA5/ANA5 RA4_AN3 EQU B'00000100' ;RA4/ANA4 RA2_AN2 EQU B'00000010' ;RA2/ANA2 RA1_AN1 EQU B'00000001' ;RA1/ANA1 RA0_AN0 EQU B'00000000' ;RA0/ANA0 READ_ADC ;Analog-to-Digital Converter In: W(Analog Select) Out:F(RADRESH,RADRESL) movlb .1 ;Bank1 movwf ADPCH ;5:0 ADC Input Channel Selection bits movlb .2 BSF ADCON0,ADON ;1 ADC is enabled 0 ADC is disabled MOVLW .20 ;Fosc=32MHz ;MOVLW .5 ;Fosc= 8MHz ;MOVLW .2 ;Fosc= 4MHz MOVWF ACQT ;Min Acquisition Time 5uS DECFSZ ACQT,F ;- GOTO $-1 ;-^ BSF ADCON0,ADGO ;1 ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the CONT bit BTFSC ADCON0,ADGO ;0 ADC conversion completed/not in progress GOTO $-1 ;-^ BCF ADCON0,ADON ;1 ADC is enabled 0 ADC is disabled movlb .1 movf ADRESH,W ;ADC Result Register MOVWF RADRESH movf ADRESL,W MOVWF RADRESL MOVLB .0 ;Bank0 RETURN ; ; SET_ADC ;Page507 movlb .2 BCF ADCON0,ADCS ;1 Clock supplied from FRC dedicated oscillator 0 Clock supplied by Fosc, divided according to ADCLK register movlw B'00000100' ;32MHz Fosc/10 Tad=500nS movwf ADCLK ;ADC Conversion Clock Select 6 bits ;MOVLW B'00000011' ;VREF+ is connected to internal Fixed Voltage Reference (FVR) module ;MOVLW B'00000010' ;VREF+ is connected to external Vref+ MOVLW B'00000000' ;VREF+ is connected to Vdd MOVWF ADREF ; BCF ADREF,4 ;1= VREF- is connected to external VREF- 0= VREF- is connected to AVss movlb .2 BCF ADCON0,ADFM0 ;1= 0 0 0 0 X X X X / x x x x x x x x 0= X X X X X X X X / x x x x 0 0 0 0 ;movlw 0x00 ; x ADC clock periods => acquisition time ;movwf ADACQH ;ADC Acquisition Time Control Register 13bit 5/8 ;movwf ADACQL ;Number of MOVLB .0 ;Bank0 RETURN ; SET_FVR ;Fixed Voltage Reference Page145 movlb .18 ;For Comparator and DAC BCF FVRCON,CDAFVR1 ;1= 4.096V 1= 2.048V 0= 1.024V 0= is OFF BCF FVRCON,CDAFVR0 ;1= 0= 1= 0= ;For ADC bsf FVRCON,ADFVR1 ;1= 4.096V 1= 2.048V 0= 1.024V 0= is OFF bcf FVRCON,ADFVR0 ;1= 0= 1= 0= BTFSS FVRCON,FVRRDY ;1 = Fixed Voltage Reference otput is ready for use NOP BSF FVRCON,FVREN ;1= FVR Enable ;BCF FVRCON,TSEN ;1 = Temperature indicator is enabled ;BCF FVRCON,TSRNG ;1 = VDD > 3.6V (High Range) 0 = VDD > 1.8V (Low Range) movlb .0 ;Bank0 RETURN ; SET_CWG1 movlb .12 clrw ;2:0 CWG Mode bits ;IORLW B'00000101' ;CWG outputs operate in Push-Pull mode IORLW B'00000100' ;CWG outputs operate in Half-Bridge mode ;IORLW B'00000011' ;CWG outputs operate in Reverse Full-Bridge mode ;IORLW B'00000010' ;CWG outputs operate in Forward Full-Bridge mode ;IORLW B'00000001' ;CWG outputs operate in Synchronous Steering mode ;IORLW B'00000000' ;CWG outputs operate in Asynchronous Steering mode movwf CWG1CON0 BSF CWG1CON0,CWG1EN ;1= Module is enabled 0= Module is disabled ; ;BCF CWG1CLK,CWG1CS ;1= HFINTOSC (remains operating during Sleep) 0= Fosc (system clock) ;BSF CWG1CON0,CWG1LD ;1= (Enable) Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit is set ;movlw 0x00 ;Death Time 1/Fosc * X =32MHz=> 0.031uS * X ;MOVWF CWG1DBR ;5:0 Rising Dead-Band Count Register (.0 - .63) ;MOVWF CWG1DBF ;5:0 Falling Edge-Triggered Dead-Band Count bits ; clrw ;3:0 CWG Output 'y' Polarity bit ;IORLW B'00000000' ;1= Signal output is inverted polarity 0= Signal output is normal polarity ;.... movwf CWG1CON1 ;btfss CWG1CON1,CWG1IN ;1= CWG input is a logic 1 0= CWG input is a logic 0 ; movlb .6 movlw B'00001100' ;CCP1 Mode PWM Operation movwf CCP1CON BSF CCP1CON,CCP1FMT ;1= PWM mode Left-aligned format XXXXXXXX XX000000 0= PWM mode Right-aligned format 000000XX XXXXXXXX BSF CCP1CON,CCP1EN ;1= CCP is enabled 0= CCP is disabled ;btfss CCP1CON,CCP1OUT ;CCP Output Data ; movlb .6 movlw 0x80 movwf CCPR1H ;Bit 9:2 bcf CCPR1L,7 ;Bit 1 bcf CCPR1L,6 ;Bit 0 movlb .0 ; movlb .12 clrw ;3:0 CWG Data Input Sources ;IORLW B'00001110' ;CLC4_out ;IORLW B'00001101' ;CLC3_out ;IORLW B'00001100' ;CLC2_out ;IORLW B'00001011' ;CLC1_out ;IORLW B'00001010' ;DSM1_out ;IORLW B'00001001' ;C2_out ;IORLW B'00001000' ;C1_out ;IORLW B'00000111' ;NCO1_out ;IORLW B'00000110' ;PWM7_out ;IORLW B'00000101' ;PWM6_out ;IORLW B'00000100' ;CCP4_out ;IORLW B'00000011' ;CCP3_out ;IORLW B'00000010' ;CCP2_out IORLW B'00000001' ;CCP1_out ;IORLW B'00000000' ;Pin selected by CWG1INPPS RA2* movwf CWG1ISM ; clrw ;3:2 Auto-Shutdown Control Register 0 ;IORLW B'00001100' ;A logic '1' is placed on CWGxA/C when an auto-shutdown event occurs. IORLW B'00001000' ;A logic '0' is placed on CWGxA/C when an auto-shutdown event occurs. ;IORLW B'00000100' ;Pin is tri-stated on CWGxA/C when an auto-shutdown event occurs. ;IORLW B'00000000' ;The Inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band interval when an auto-shutdown event occurs. ;5:4 ;IORLW B'00110000' ;A logic '1' is placed on CWGxB/D when an auto-shutdown event occurs. IORLW B'00100000' ;A logic '0' is placed on CWGxB/D when an auto-shutdown event occurs. ;IORLW B'00010000' ;Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs. ;IORLW B'00000000' ;The Inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band interval when an auto-shutdown event occurs. movwf CWG1AS0 BCF CWG1AS0,CWG1REN ;1= Auto-restart is enabled 0= Auto-restart is disabled BCF CWG1AS0,CWG1SHUTDOWN ;1= An auto-shutdown state is in effect 0= No auto-shutdown event has occurred ;CWG Auto-shutdown Source 1= Enabled 0= Disabled ;BCF CWG1AS1,AS6E ;CLC2_out/CLC3_out (low causes shutdown) ;BCF CWG1AS1,AS5E ;CMP2_out (low causes shutdown) ;BCF CWG1AS1,AS4E ;CMP1_out (low causes shutdown) ;BCF CWG1AS1,AS3E ;TMR6_postscaled (high causes shutdown) ;BCF CWG1AS1,AS2E ;TMR4_postscaled (high causes shutdown) ;BCF CWG1AS1,AS1E ;TMR2_postscaled (high causes shutdown) ;BSF CWG1AS1,AS0E ;Pin selected by CWGxPPS (low causes shutdown) ;movlb .61 ;MOVLW B'00000010' ;RA2 ;4:3 PORTabc 2:0 Pin ;MOVWF CWG1PPS ;movlb .12 ; ;Steering Data OVR'y' bit ;BCF CWG1STR,CWG1STRA ;1= CWGx'y' output has the CWG data input waveform with polarity control from POLy bit ;BCF CWG1STR,CWG1STRB ;0= CWGx'y' output is assigned to value of OVRy bit ;BCF CWG1STR,CWG1STRC ; ;BCF CWG1STR,CWG1STRD ; ;BCF CWG1STR,CWG1OVRA ;1= STRy = 0 and POLy = x CWGx'y' output is high ;BCF CWG1STR,CWG1OVRB ;0= STRy = 0 and POLy = x CWGx'y' output is low ;BCF CWG1STR,CWG1OVRC ; ;BCF CWG1STR,CWG1OVRD ; ; movlb .4 ;TMR2 TMR4 TMR6 in PWM1 mode CCP Timers Selection Register0 BCF CCPTMRS0,1 ;0 1 1 BSF CCPTMRS0,0 ;1 0 1 CALL SET_TMR2 movlb .5 movlw 0xFF movwf T2PR CLRF T2TMR ;Bank5 movlb .14 BCF PIR4,TMR2IF ; BTFSS PIR4,TMR2IF ;New PWM cycle? GOTO $-1 ; movlb .0 ; movlb .62 ;SET_PPS Output Page236 movlw B'00000101' ;CWG1A movwf RC5PPS ;Pin 5 <=> PIC16F1829 movlw B'00000110' ;CWG1B movwf RC4PPS ;Pin 6 ;movlw B'00000111' ;CWG1C ;movwf RC3PPS ;Pin 7 RC3 ;movwf RC1PPS ;RC1 ;movlw B'00001000' ;CWG1D ;movwf RC2PPS ;Pin 14 ;movwf RC0PPS ;RC0 ; movlb .0 BCF TRISC,5 ;CWG1A = RC5 Output! BCF TRISC,4 ;CWG1B = RC4 Output! ;BCF TRISC,3 ;CWG1C = RC3/RC1 Output! ;BCF TRISC,2 ;CWG1D = RC2/RC0 Output! RETURN ; SET_CWG2 movlb .12 clrw ;2:0 CWG Mode bits ;IORLW B'00000101' ;CWG outputs operate in Push-Pull mode IORLW B'00000100' ;CWG outputs operate in Half-Bridge mode ;IORLW B'00000011' ;CWG outputs operate in Reverse Full-Bridge mode ;IORLW B'00000010' ;CWG outputs operate in Forward Full-Bridge mode ;IORLW B'00000001' ;CWG outputs operate in Synchronous Steering mode ;IORLW B'00000000' ;CWG outputs operate in Asynchronous Steering mode movwf CWG2CON0 BSF CWG2CON0,CWG2EN ;1= Module is enabled 0= Module is disabled ; ;BCF CWG2CLK,CWG2CS ;1= HFINTOSC (remains operating during Sleep) Fosc (system clock) ;BSF CWG2CON0,CWG2LD ;1= Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit is set ;movlw 0x00 ;Death Time 1/Fosc * X =32MHz=> 0.031uS * X ;movwf CWG2DBR ;5:0 Rising Dead-Band Count Register (.0 - .63) ;movwf CWG2DBF ;5:0 Falling Edge-Triggered Dead-Band Count bits ; clrw ;3:0 CWG Output 'y' Polarity bit ;IORLW B'00000000' ;1= Signal output is inverted polarity 0= Signal output is normal polarity ;.... movwf CWG2CON1 ;btfss CWG2CON1,CWG2IN ;1= CWG input is a logic 1 0= CWG input is a logic 0 ; movlb .6 movlw B'00001100' ;CCP2 Mode PWM Operation movwf CCP2CON BSF CCP2CON,CCP2FMT ;1= PWM mode Left-aligned format XXXXXXXX XX000000 0= PWM mode Right-aligned format 000000XX XXXXXXXX BSF CCP2CON,CCP2EN ;1= CCP is enabled 0= CCP is disabled ;btfss CCP2CON,CCP2OUT ;CCP Output Data ; movlb .6 movlw 0x80 movwf CCPR2H ;Bit 9:2 bcf CCPR2L,7 ;Bit 1 bcf CCPR2L,6 ;Bit 0 movlb .0 ; movlb .12 clrw ;3:0 CWG Data Input Sources ;IORLW B'00001110' ;CLC4_out ;IORLW B'00001101' ;CLC3_out ;IORLW B'00001100' ;CLC2_out ;IORLW B'00001011' ;CLC1_out ;IORLW B'00001010' ;DSM1_out ;IORLW B'00001001' ;C2_out ;IORLW B'00001000' ;C1_out ;IORLW B'00000111' ;NCO1_out ;IORLW B'00000110' ;PWM7_out ;IORLW B'00000101' ;PWM6_out ;IORLW B'00000100' ;CCP4_out ;IORLW B'00000011' ;CCP3_out IORLW B'00000010' ;CCP2_out ;IORLW B'00000001' ;CCP1_out ;IORLW B'00000000' ;Pin selected by CWG1INPPS RA2* movwf CWG2ISM clrw ;3:2 Auto-Shutdown Control Register 0 ;IORLW B'00001100' ;A logic '1' is placed on CWGxA/C when an auto-shutdown event occurs. IORLW B'00001000' ;A logic '0' is placed on CWGxA/C when an auto-shutdown event occurs. ;IORLW B'00000100' ;Pin is tri-stated on CWGxA/C when an auto-shutdown event occurs. ;IORLW B'00000000' ;The Inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band interval when an auto-shutdown event occurs. ;5:4 ;IORLW B'00110000' ;A logic '1' is placed on CWGxB/D when an auto-shutdown event occurs. IORLW B'00100000' ;A logic '0' is placed on CWGxB/D when an auto-shutdown event occurs. ;IORLW B'00010000' ;Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs. ;IORLW B'00000000' ;The Inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band interval when an auto-shutdown event occurs. movwf CWG2AS0 BCF CWG2AS0,CWG2REN ;1= Auto-restart is enabled 0= Auto-restart is disabled BCF CWG2AS0,CWG2SHUTDOWN ;1= An auto-shutdown state is in effect 0= No auto-shutdown event has occurred ;CWG Auto-shutdown Source 1= Enabled 0= Disabled ;BCF CWG2AS1,AS6E ;CLC2_out/CLC3_out (low causes shutdown) ;BCF CWG2AS1,AS5E ;CMP2_out (low causes shutdown) ;BCF CWG2AS1,AS4E ;CMP1_out (low causes shutdown) ;BCF CWG2AS1,AS3E ;TMR6_postscaled (high causes shutdown) ;BCF CWG2AS1,AS2E ;TMR4_postscaled (high causes shutdown) ;BCF CWG2AS1,AS1E ;TMR2_postscaled (high causes shutdown) ;BSF CWG2AS1,AS0E ;Pin selected by CWGxPPS (low causes shutdown) ;movlb .61 ;MOVLW B'00000010' ;RA2 ;4:3 PORTabc 2:0 Pin ;MOVWF CWG2PPS ;movlb .12 ;Steering Data OVR'y' bit ;BCF CWG2STR,CWG2STRA ;1= CWGx'y' output has the CWG data input waveform with polarity control from POLy bit ;BCF CWG2STR,CWG2STRB ;0= CWGx'y' output is assigned to value of OVRy bit ;BCF CWG2STR,CWG2STRC ; ;BCF CWG2STR,CWG2STRD ; ;BCF CWG2STR,CWG2OVRA ;1= STRy = 0 and POLy = x CWGx'y' output is high ;BCF CWG2STR,CWG2OVRB ;0= STRy = 0 and POLy = x CWGx'y' output is low ;BCF CWG2STR,CWG2OVRC ; ;BCF CWG2STR,CWG2OVRD ; ; movlb .4 ;TMR2 TMR4 TMR6 in PWM2 mode CCP Timers Selection Register0 BSF CCPTMRS0,3 ;0 1 1 BCF CCPTMRS0,2 ;1 0 1 CALL SET_TMR4 movlb .5 movlw 0xFF movwf T4PR CLRF T4TMR movlb .14 BCF PIR4,TMR4IF ; BTFSS PIR4,TMR4IF ;New PWM cycle? GOTO $-1 ; ; movlb .62 ;SET_PPS Output Page236 movlw B'00011011' ;CWG2A movwf RC3PPS ;Pin 7 movlw B'00011100' ;CWG2B movwf RC2PPS ;Pin 14 ;movlw B'00011101' ;CWG2C ;movlw B'00011110' ;CWG2D ; movlb .0 ;Bank0 BCF TRISC,3 ;CWG2A = RC3/RA5 Output! BCF TRISC,2 ;CWG2B = RC2/RA4 Output! RETURN ; SET_PWM6 ;PWM6 10bit Pulse Width Modulation movlb .4 ;TMR2 TMR4 TMR6 in PWM6 mode CCP Timers Selection Register0 BCF CCPTMRS1,3 ;0 1 1 BSF CCPTMRS1,2 ;1 0 1 movlb .0 MOVLB .7 ;Page BCF PWM6CON,PWM6POL ;1= PWM output is inverted 0= PWM output is normal BCF PWM6CON,PWM6EN ;1= PWM module is enabled 0= PWM module is disabled ;btfss PWM6CON,PWM6OUT ;PWM Module Output Level When Bit is Read movlb .0 MOVLB .7 movlw 0x80 movwf PWM6DCH ;Bit 9 - 2 bcf PWM6DCL,PWM6DC1 ;Bit 1 bcf PWM6DCL,PWM6DC0 ;Bit 0 movlb .0 ; CALL SET_TMR2 ; movlb .5 ;Bank5 movlw 0xFF movwf T2PR CLRF T2TMR movlb .14 BCF PIR4,TMR2IF ; BTFSS PIR4,TMR2IF ;New PWM cycle? GOTO $-1 ; ; movlb .62 ;SET_PPS Output Page236 movlw B'00001101' ;PWM6OUT ;movwf RA0PPS ;movwf RA1PPS movwf RA2PPS ;movwf RA4PPS ;movwf RA5PPS ;movwf RB4PPS ;movwf RB5PPS ;movwf RB6PPS ;movwf RB7PPS ;movwf RC0PPS ;movwf RC1PPS ;movwf RC6PPS ;movwf RC7PPS movlb .0 bcf TRISA,2 ;Output! RETURN ; SET_PWM7 movlb .4 ;TMR2 TMR4 TMR6 in PWM6 mode CCP Timers Selection Register0 BCF CCPTMRS1,5 ;0 1 1 BSF CCPTMRS1,4 ;1 0 1 movlb .0 movlb .62 ;SET_PPS Output Page236 movlw B'00001110' ;PWM7OUT ;movwf RA0PPS ;movwf RA1PPS ;movwf RA2PPS ;movwf RA4PPS ;movwf RA5PPS ;movwf RB4PPS ;movwf RB5PPS ;movwf RB6PPS ;movwf RB7PPS ;movwf RC0PPS ;movwf RC1PPS ;movwf RC2PPS ;movwf RC3PPS ;movwf RC4PPS ;movwf RC5PPS ;movwf RC6PPS ;movwf RC7PPS movlb .0 BCF TRISC,6 ;RC6 Output! RETURN ; SET_WDT ;Page 167 MOVLB .16 MOVLW B'00001011' ;1:65536 1mS to 256S MOVWF WDTCON0 ;5:0 BSF WDTCON0,SEN ;1=WDT Is Turned ON (If Configuration 2007h Enable*) 0=WDT Is Turned OFF clrw ;6:4 ;IORLW B'00010000' ;MFINTOSC 31.25 kHz IORLW B'00000000' ;LFINTOSC 31 kHz ;2:0 Watchdog Timer Window Select bits IORLW B'00000111' ; 100% ;IORLW B'00000110' ;12.5 87.5 ;IORLW B'00000101' ;25 75 ;IORLW B'00000100' ;37.5 62.5 ;IORLW B'00000011' ;50 50 ;IORLW B'00000010' ;62.5 37.5 ;IORLW B'00000001' ;75 25 ;IORLW B'00000000' ;87.5 12.5 movwf WDTCON1 ;movf WDTPSL,W ;16bit Prescale Select Low Register (Read-Only) ;movf WDTPSH,W movf WDTTMR,W ;Timer Register (Read-Only) MOVLB .0 ;Bank0 RETURN ; SET_TMR0 ;Page movlb .11 clrw ;3:0 TMR0 Output Postscaler (Divider) Select ;IORLW B'00001111' ;1:16 ;... ;IORLW B'00000000' ;1:1 movwf T0CON0 BSF T0CON0,T016BIT ;1= TMR0 is a 16-bit timer 0= TMR0 is an 8-bit timer (0 to TMR0H) BSF T0CON0,T0EN ;1= The module is enabled and operating clrw ;7:5 Clock Source Select ;IORLW B'11100000' ;CLC1_out ;IORLW B'11000000' ;SOSC ;IORLW B'10100000' ;MFINTOSC(500 kHz) ;IORLW B'10000000' ;LFINTOSC IORLW B'01100000' ;HFINTOSC ;IORLW B'01000000' ;FOSC/4 ;IORLW B'00100000' ;Pin selected by T0CKIPPS (Inverted) ;IORLW B'00000000' ;Pin selected by T0CKIPPS (Noninverted) ;3:0 Prescaler Rate Select ;IORLW B'00001111' ;1:32768 ;IORLW B'00001110' ;1:16384 ;IORLW B'00001101' ;1:8192 ;IORLW B'00001100' ;1:4096 ;IORLW B'00001011' ;1:2048 ;IORLW B'00001010' ;1:1024 ;IORLW B'00001001' ;1:512 IORLW B'00001000' ;1:256 ;IORLW B'00000111' ;1:128 ;IORLW B'00000110' ;1:64 INTOSC/64 32MHz => 2uS ;IORLW B'00000101' ;1:32 ;IORLW B'00000100' ;1:16 ;IORLW B'00000011' ;1:8 ;IORLW B'00000010' ;1:4 ;IORLW B'00000001' ;1:2 ;IORLW B'00000000' ;1:1 movwf T0CON1 BCF T0CON1,T0ASYNC ;1= The input to the TMR0 counter is not synchronized to system clocks ;0= The input to the TMR0 counter is synchronized to FOSC/4 movlb .0 ;Bank0 RETURN ; SET_TMR1 ;Timer1 Module: Max period 8uS * 65536 = 524,288mS (Fosc=4MHz) Page movlb .4 clrw ;Timer Clock Source Selection Register ;IORLW B'00010000' ;CLC4_out ;IORLW B'00001111' ;CLC3_out ;IORLW B'00001110' ;CLC2_out ;IORLW B'00001101' ;CLC1_out ;IORLW B'00001100' ;Timer5 overflow output ;IORLW B'00001011' ;Timer3 overflow output ;IORLW B'00001010' ;Reserved ;IORLW B'00001001' ;Timer0 overflow output ;IORLW B'00001000' ;CLKR output ;IORLW B'00000111' ;SOSC ;IORLW B'00000110' ;MFINTOSC ;IORLW B'00000101' ;MFINTOSC ;IORLW B'00000100' ;LFINTOSC ;IORLW B'00000011' ;HFINTOSC ;IORLW B'00000010' ;FOSC IORLW B'00000001' ;FOSC/4 ;IORLW B'00000000' ;T1CKIPPS movwf TMR1CLK BSF T1CON,T1CKPS1 ;Timer prescaler 1= /8 1= /4 0= /2 0= /1 BSF T1CON,T1CKPS0 ;Timer prescaler 1 0 1 0 BSF T1CON,NOT_T1SYNC ;1= Do not synchronize external clock input BSF T1CON,T1RD16 ;1= Enables register read/write of Timer in one 16-bit operation 0= two 8-bit operations BSF T1CON,TMR1ON ;1=Enables Timer1 0=Stop Timer1 ;Page289 BCF T1GCON,T1GE ;1= Gate Control 0= Always Counting ;T1GCON,T1GVAL ;T1GCON,T1GGO ;T1GCON,T1GSPM ;T1GCON,T1GTM ;T1GCON,T1GPOL ;movwf TMR1GATE ;Timer Gate Source Selection Register movlb .0 RETURN ; SET_TMR2 movlb .5 movlw B'00000000' ;4:0 TMR2 Operating Modes Page 296 movwf T2HLT BCF T2HLT,T2CKSYNC ;1= ON bit is synchronized to timer clock input 0= ON bit is not synchronized to timer clock input BCF T2HLT,T2CKPOL ;1= Falling edge of input clock clocks timer/prescaler 0= Rising edge of input clock clocks timer/prescaler BCF T2HLT,T2PSYNC ;1= Timer Prescaler Output is synchronized to FOSC/4 0= Timer Prescaler Output is not synchronized to FOSC/4 clrw ;External Reset Source Selection Bits ;IORLW B'00001101' ;CLC4_out ;IORLW B'00001100' ;CLC3_out ;IORLW B'00001011' ;CLC2_out ;IORLW B'00001010' ;CLC1_out ;IORLW B'00001001' ;ZCD1_output ;IORLW B'00001000' ;C2OUT_sync ;IORLW B'00000111' ;C1OUT_sync ;IORLW B'00000110' ;PWM7_out ;IORLW B'00000101' ;PWM6_out ;IORLW B'00000100' ;CCP4_out ;IORLW B'00000011' ;CCP3_out ;IORLW B'00000010' ;CCP2_out ;IORLW B'00000001' ;CCP1_out IORLW B'00000000' ;T2INPPS movwf T2RST clrw ;Timer Clock Source Selection bits ;IORLW B'00001110' ;CLC4_out ;IORLW B'00001101' ;CLC3_out ;IORLW B'00001100' ;CLC2_out ;IORLW B'00001011' ;CLC1_out ;IORLW B'00001010' ;ZCD1_output ;IORLW B'00001001' ;NCO1_out ;IORLW B'00001000' ;CLKR ;IORLW B'00000111' ;SOSC ;IORLW B'00000110' ;MFINTOSC(31.25 kHz) ;IORLW B'00000101' ;MFINTOSC(500 kHz) ;IORLW B'00000100' ;LFINTOSC ;IORLW B'00000011' ;HFINTOSC(32 MHz) ;IORLW B'00000010' ;FOSC IORLW B'00000001' ;FOSC/4 ;IORLW B'00000000' ;T2CKIPPS movwf T2CLKCON clrw ;6:4 Timer Clock Prescale Select bits ;IORLW B'01110000' ;1:128 Prescaler ;IORLW B'01100000' ;1:64 Prescaler ;IORLW B'01010000' ;1:32 Prescaler ;IORLW B'01000000' ;1:16 Prescaler ;IORLW B'00110000' ;1:8 Prescaler ;IORLW B'00100000' ;1:4 Prescaler ;IORLW B'00010000' ;1:2 Prescaler IORLW B'00000000' ;1:1 Prescaler ;3:0 Timer Output Postscaler Select bits ;IORLW B'00001111' ;1:16 Postscaler ;IORLW B'00001110' ;1:15 Postscaler ;IORLW B'00001101' ;1:14 Postscaler ;IORLW B'00001100' ;1:13 Postscaler ;IORLW B'00001011' ;1:12 Postscaler ;IORLW B'00001010' ;1:11 Postscaler ;IORLW B'00001001' ;1:10 Postscaler ;IORLW B'00001000' ;1:9 Postscaler ;IORLW B'00000111' ;1:8 Postscaler ;IORLW B'00000110' ;1:7 Postscaler ;IORLW B'00000101' ;1:6 Postscaler ;IORLW B'00000100' ;1:5 Postscaler ;IORLW B'00000011' ;1:4 Postscaler ;IORLW B'00000010' ;1:3 Postscaler ;IORLW B'00000001' ;1:2 Postscaler IORLW B'00000000' ;1:1 Postscaler movwf T2CON BSF T2CON,T2ON ;1= Timer is on 0= Timer is off: all counters and state machines are reset movlb .0 RETURN ; SET_TMR4 movlb .5 movlw B'00000000' ;4:0 TMR4 Operating Modes Page 296 movwf T4HLT BCF T4HLT,T4CKSYNC ;1= ON bit is synchronized to timer clock input 0= ON bit is not synchronized to timer clock input BCF T4HLT,T4CKPOL ;1= Falling edge of input clock clocks timer/prescaler 0= Rising edge of input clock clocks timer/prescaler BCF T4HLT,T4PSYNC ;1= Timer Prescaler Output is synchronized to FOSC/4 0= Timer Prescaler Output is not synchronized to FOSC/4 ; clrw ;External Reset Source Selection Bits ;IORLW B'00001101' ;CLC4_out ;IORLW B'00001100' ;CLC3_out ;IORLW B'00001011' ;CLC2_out ;IORLW B'00001010' ;CLC1_out ;IORLW B'00001001' ;ZCD1_output ;IORLW B'00001000' ;C2OUT_sync ;IORLW B'00000111' ;C1OUT_sync ;IORLW B'00000110' ;PWM7_out ;IORLW B'00000101' ;PWM6_out ;IORLW B'00000100' ;CCP4_out ;IORLW B'00000011' ;CCP3_out ;IORLW B'00000010' ;CCP2_out ;IORLW B'00000001' ;CCP1_out IORLW B'00000000' ;T2INPPS movwf T4RST clrw ;Timer Clock Source Selection bits ;IORLW B'00001110' ;CLC4_out ;IORLW B'00001101' ;CLC3_out ;IORLW B'00001100' ;CLC2_out ;IORLW B'00001011' ;CLC1_out ;IORLW B'00001010' ;ZCD1_output ;IORLW B'00001001' ;NCO1_out ;IORLW B'00001000' ;CLKR ;IORLW B'00000111' ;SOSC ;IORLW B'00000110' ;MFINTOSC(31.25 kHz) ;IORLW B'00000101' ;MFINTOSC(500 kHz) ;IORLW B'00000100' ;LFINTOSC ;IORLW B'00000011' ;HFINTOSC(32 MHz) ;IORLW B'00000010' ;FOSC IORLW B'00000001' ;FOSC/4 ;IORLW B'00000000' ;T2CKIPPS movwf T4CLKCON clrw ;6:4 Timer Clock Prescale Select bits ;IORLW B'01110000' ;1:128 Prescaler ;IORLW B'01100000' ;1:64 Prescaler ;IORLW B'01010000' ;1:32 Prescaler ;IORLW B'01000000' ;1:16 Prescaler ;IORLW B'00110000' ;1:8 Prescaler ;IORLW B'00100000' ;1:4 Prescaler ;IORLW B'00010000' ;1:2 Prescaler IORLW B'00000000' ;1:1 Prescaler ;3:0 Timer Output Postscaler Select bits ;IORLW B'00001111' ;1:16 Postscaler ;IORLW B'00001110' ;1:15 Postscaler ;IORLW B'00001101' ;1:14 Postscaler ;IORLW B'00001100' ;1:13 Postscaler ;IORLW B'00001011' ;1:12 Postscaler ;IORLW B'00001010' ;1:11 Postscaler ;IORLW B'00001001' ;1:10 Postscaler ;IORLW B'00001000' ;1:9 Postscaler ;IORLW B'00000111' ;1:8 Postscaler ;IORLW B'00000110' ;1:7 Postscaler ;IORLW B'00000101' ;1:6 Postscaler ;IORLW B'00000100' ;1:5 Postscaler ;IORLW B'00000011' ;1:4 Postscaler ;IORLW B'00000010' ;1:3 Postscaler ;IORLW B'00000001' ;1:2 Postscaler IORLW B'00000000' ;1:1 Postscaler movwf T4CON BSF T4CON,T4ON ;1= Timer is on 0= Timer is off: all counters and state machines are reset movlb .0 RETURN ; SET_INT_DISABLE ;Page CLRF INTCON MOVLB .14 ;Bank14 CLRF PIE0 CLRF PIE1 CLRF PIE2 CLRF PIE3 CLRF PIE4 CLRF PIE5 CLRF PIE6 CLRF PIE7 CLRF PIE8 MOVLB .0 ;Select Bank0. RETURN SET_INT_PORTCHANGE ;Page MOVLB .62 ;Bank62 MOVLW B'00000000' ;7 6 IOCAx5 IOCAx4 IOCAx3 IOCAx2 IOCAx1 IOCAx0 MOVWF IOCAP ;1=Interrupt-on-change Positive Enabled 0=Interrupt-on-change Positive Disabled MOVLW B'00000000' ;7 6 IOCAx5 IOCAx4 IOCAx3 IOCAx2 IOCAx1 IOCAx0 MOVWF IOCAN ;1=Interrupt-on-change Negative Enabled 0=Interrupt-on-change Negative Disabled MOVLW B'00000000' ;IOCBx7 IOCBx6 IOCBx5 IOCBx4 3 2 1 0 MOVWF IOCBP ;1=Interrupt-on-change Positive Enabled 0=Interrupt-on-change Positive Disabled MOVLW B'00000000' ;IOCBx7 IOCBx6 IOCBx5 IOCBx4 3 2 1 0 MOVWF IOCBN ;1=Interrupt-on-change Negative Enabled 0=Interrupt-on-change Negative Disabled CLRF IOCAF ;PORTA Interrupt-on-Change Flag Register 0= No change was detected, or the user cleared the detected change CLRF IOCBF ;PORTB Interrupt-on-Change Flag Register 0= No change was detected, or the user cleared the detected change MOVLB .14 ;Bank14 BCF PIR0,IOCIF ;PORTA/PORTB Change Interrupt Global Flag BSF PIE0,IOCIE ;1=PORTA/PORTB Change Interrupt Enables 0=PORTA/PORTB Change Interrupt Disable MOVLB .0 ;Bank0 BSF INTCON,PEIE ;1=Enables All Peripheral Interrupts 0=Disables All Peripheral Interrupts RETURN SET_INT_EXTINT ;Page Pin RA2 BCF INTCON,INTEDG ;1= Rising RA2/INT Interrupt 0= Falling RA2/INT Interrupt MOVLB .14 ;Bank14 BCF PIR0,INTF ;RA2/INT Change Interrupt Flag BSF PIE0,INTE ;1=RA2/INT Change Interrupt Enables 0=RA2/INT Change Interrupt Disable MOVLB .0 ;Bank0 BSF INTCON,PEIE ;1=Enables All Peripheral Interrupts 0=Disables All Peripheral Interrupts RETURN SET_INT_TMR0 MOVLB .14 ;Bank14 BCF PIR0,TMR0IF ;TMR1 Overflow Interrupt Flag BSF PIE0,TMR0IE ;1=Enables TMR0 Overflow Interrupt 0=Disables TMR0 Overflow Interrupt MOVLB .0 ;Bank0 BSF INTCON,PEIE ;1=Enables All Peripheral Interrupts 0=Disables All Peripheral Interrupts RETURN SET_INT_TMR1 MOVLB .14 ;Bank14 BCF PIR4,TMR1IF ;TMR1 Overflow Interrupt Flag BSF PIE4,TMR1IE ;1=Enables TMR1 Overflow Interrupt 0=Disables TMR1 Overflow Interrupt MOVLB .0 ;Bank0 BSF INTCON,PEIE ;1=Enables All Peripheral Interrupts 0=Disables All Peripheral Interrupts RETURN ; SET_OSC ;Oscillator configuration. movlb .17 ;Bank17 clrw ;6:4 NOSC New Oscillator Source Request bits ;IORLW B'01110000' ;EXTOSC IORLW B'01100000' ;HFINTOSC ;IORLW B'01010000' ;LFINTOSC ;IORLW B'01100000' ;SOSC Secondary oscillator ;IORLW B'00100000' ;EXTOSC + 4x PLL ;IORLW B'00010000' ;HFINTOSC + 2x PLL ;3:0 NDIV New Divider Selection Request bits IORLW B'00000000' ;/1 Clock Divider ;.... movwf OSCCON1 clrw ;2:0 NOSC = 110 NOSC = 001 = 2xPLL HFINTOSC Frequency Selection Register IORLW B'00000110' ; 32MHz Reserved ;IORLW B'00000101' ; 16MHz 32MHz ;IORLW B'00000100' ; 12MHz 24MHz ;IORLW B'00000011' ; 8MHz 16MHz ;IORLW B'00000010' ; 4MHz Reserved ;IORLW B'00000001' ; 2MHz Reserved ;IORLW B'00000000' ; 1MHz Reserved movwf OSCFRQ ;movf OSCCON2,W ;Current Oscillator Source Select bits (read-only) ;Current Divider Select bits (read-only) ;BCF OSCCON3,CSWHOLD ;1= Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready ;0= Clock switch may proceed when the oscillator selected by NOSC is ready; when NOSCR becomes 1,the switch will occur ;BCF OSCCON3,SOSCPWR ;1= Secondary oscillator operating in High-Power mode ;0= Secondary oscillator operating in Low-Power mode ;BTFSS OSCCON3,NOSCR ;0= A clock switch is in progress ;goto $-1 ;BTFSS OSCCON3,ORDY ;New Oscillator is Ready bit (read-only) ;BTFSS OSCSTAT,PLLR ;1= The oscillator is ready to be used ;BTFSS OSCSTAT,ADOR ;0= The oscillator is not enabled, or is not yet ready to be used ;BTFSS OSCSTAT,SOR ;BTFSS OSCSTAT,LFOR ;BTFSS OSCSTAT,MFOR ;BTFSS OSCSTAT,HFOR ;BTFSS OSCSTAT,EXTOR ;Oscillator Manual Enable Register ;BCF OSCEN,EXTOEN ;1= EXTOSC is explicitly enabled, operating as specified by CONFIG1[FEXTOSC] ;0= EXTOSC is only enabled if requested by a peripheral ;BCF OSCEN,HFOEN ;1= HFINTOSC is explicitly enabled, operating as specified by OSCFRQ ;0= HFINTOSC is only enabled if requested by a peripheral ;BCF OSCEN,MFOEN ;1= MFINTOSC is explicitly enabled (500 kHz/31.25 kHz) ;0= MFINTOSC is only enabled if requested by a peripheral ;BCF OSCEN,LFOEN ;1= LFINTOSC is explicitly enabled (31 kHz) ;0= LFINTOSC is only enabled if requested by a peripheral ;BCF OSCEN,SOSCEN ;1= Secondary Oscillator is explicitly enabled, operating as specified by SOSCPWR ;0= Secondary Oscillator is only enabled if requested by a peripheral ;BCF OSCEN,ADOEN ;1 ADC oscillator is explicitly enabled ;0 ADC oscillator is only enabled if requested by a peripheral MOVLW OSCTUNE_MNL ;Central frequency MOVWF OSCTUNE ; MOVLB .0 ;Bank0 RETURN ; ; SET_IO ;Настройка на портовете In, Out, Analog, Pull-up CLRF LATA ;Page Output Latch CLRF LATB CLRF LATC movlb .62 ;Bank62 1= Analog Input 0= Digital I/O MOVLW B'00000000' ;X X ANA5 ANA4 X ANA2 ANA1 ANA0 MOVWF ANSELA ;X X RA5 RA4 RA3 RA2 RA1 RA0 MOVLW B'00000000' ;ANB7 ANB6 ANB5 ANB4 X X X X MOVWF ANSELB ;RB7 RB6 RB5 RB4 X X X X MOVLW B'00000000' ;ANC7 ANC6 ANC5 ANC4 ANC3 ANC2 ANC1 ANC0 MOVWF ANSELC ;RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 ;1= ST Input 0= TTL Input MOVLW B'00000000' ; MOVWF INLVLA ;X X RA5 RA4 RA3 RA2 RA1 RA0 MOVLW B'00000000' MOVWF INLVLB ;RB7 RB6 RB5 RB4 X X X X MOVLW B'00000000' MOVWF INLVLC ;RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 ;Slew Rate Control Register ;MOVLW B'00000000' ;X X SLRA5 SLRA4 X SLRA2 SLRA1 SLRA0 ;MOVWF SLRCONA ;1= PORT pin slew rate is limited ;MOVLW B'00000000' ;SLRB7 SLRB6 SLRB5 SLRB4 X X X X ;MOVWF SLRCONB ;0= PORT pin slews at maximum rate ;MOVLW B'00000000' ;SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 ;MOVWF SLRCONC ; ;MOVWF ODCONA ;Open-Drain Configuration ;MOVWF ODCONB ;1= PORT pin operates as open-drain drive (sink current only) ;MOVWF ODCONC ;0= PORT pin operates as standard push-pull drive (source and sink current) ;Bank62 1=Pull-up Enable 0=Pull-up Disabled MOVLW B'00000000' ; MOVWF WPUA ; MOVLW B'00000000' ; MOVWF WPUB ; MOVLW B'00000000' ; MOVWF WPUC ; MOVLB .0 ;Bank0 MOVLW B'00111111' ;1=Input 0=Output MOVWF TRISA ;PortA<5:0> MOVLW B'11110000' ; MOVWF TRISB ;PortB<7:4> MOVLW B'11111111' ; MOVWF TRISC ;PortC<7:0> RETURN ;********************************************************************** ;*******Първоначална настройка на микроконтролера********************** START MOVLB .0 ;Bank0 clrf BSR ;Bank0 clrf PCLATH ;0- Work. Page0 CALL SET_INT_DISABLE ;Забранява всички прекъсвания. CLRF PORTA CLRF PORTB CLRF PORTC CALL SET_OSC ;OK Oscillator configuration !!! CALL SET_IO ;OK Настройка на портовете In, Out, Analog, Pull-up !!! ;CALL SET_TMR0 ;OK Настройка на Timer0 16bit / 8bit ;CALL SET_TMR1 ;Настройка на Timer1 ;Настройка на Timer3,Timer5 (като SET_TMR1) ;CALL SET_TMR2 ;OK ;CALL SET_TMR4 ;OK ;CALL SET_WDT ; ;CALL SET_INT_PORTCHANGE ;CALL SET_INT_EXTINT ;CALL SET_INT_TMR0 ;OK ;CALL SET_INT_TMR1 ;BSF INTCON,GIE ;1=Enables All Interrupts 0=Disables All Interrupts ;CALL SET_CWG1 ;OK Enable PWM - RC5,RC4,RC3,RC2 Use TMR2 ;CALL SET_CWG2 ;OK Enable PWM - RC3,RC2 Use TMR4 ;CALL SET_PWM6 ;10bit PWM RA2* Use TMR2 ;CALL SET_PWM7 ;??? като SET_PWM6 ;CALL SET_ADC ;12bit ;;; ;CALL SET_FVR ;??? Fixed Voltage Reference ;CALL SET_COMPM ;???Настройка на компаратoрите. ;CALL SET_DAC ;DAC 5bit ;CALL SET_ZCD ;??? Zero-Cross Detection Module ;CALL SET_UART ;???Set RX/TX Baud Rates Asynchronous Modes ;CALL SET_SPI1 ;??? ;CALL SET_SPI2 ;???не готова ;CALL SET_NCO ;??? GOTO BEGIN ;--^ ;********************************************************************** ORG 0x0800 ;Page1 ORG 0x1000 ;Page2 ORG 0x1800 ;Page3 ORG 0x2000 ;Page4 ORG 0x2800 ;Page5 ORG 0x3000 ;Page6 ORG 0x3800 ;Page7 END ;0x3FFF SET_PPS_OUT movlb .62 ;SET_PPS Output Page236 movlw B'00100000' ;ADCGRDB X X movlw B'00011111' ;ADCGRDA X X movlw B'00011110' ;CWG2D X X movlw B'00011101' ;CWG2C X X movlw B'00011100' ;CWG2B X X movlw B'00011011' ;CWG2A X X movlw B'00011010' ;DSM1OUT X X movlw B'00011001' ;CLKR X X movlw B'00011000' ;NCO1OUT X X movlw B'00010111' ;TMR0OUT X X movlw B'00010100' ;SDO1/SDA1 X X movlw B'00010011' ;SCK1/SCL1 X X movlw B'00010010' ;C2OUT X X movlw B'00010001' ;C1OUT X X movlw B'00010000' ;DT1 X X movlw B'00001111' ;CK1/TX1 X X movlw B'00001110' ;PWM7OUT X X movlw B'00001101' ;PWM6OUT X X movlw B'00001100' ;CCP4OUT X X movlw B'00001011' ;CCP3OUT X X movlw B'00001010' ;CCP2OUT X X movlw B'00001001' ;CCP1OUT X X movlw B'00001000' ;CWG1D X X movlw B'00000111' ;CWG1C X X movlw B'00000110' ;CWG1B X X movlw B'00000101' ;CWG1A X X movlw B'00000100' ;CLC4OUT X X movlw B'00000011' ;CLC3OUT X X movlw B'00000010' ;CLC2OUT X X movlw B'00000001' ;CLC1OUT movwf RA0PPS movwf RA1PPS movwf RA2PPS movwf RA4PPS movwf RA5PPS movwf RB4PPS movwf RB5PPS movwf RB6PPS movwf RB7PPS movwf RC0PPS movwf RC1PPS movwf RC2PPS movwf RC3PPS movwf RC4PPS movwf RC5PPS movwf RC6PPS movwf RC7PPS movlb .0 RETURN ; SET_PPS_IN movlb .61 ;SET_PPS Output Page236 ;BCF PPSLOCK,0 clrw IORLW B'00010000' ;PORTC IORLW B'00001000' ;PORTB IORLW B'00000000' ;PORTA IORLW B'00000111' ;Rx7 IORLW B'00000110' ;Rx6 IORLW B'00000101' ;Rx5 IORLW B'00000100' ;Rx4 IORLW B'00000011' ;Rx3 IORLW B'00000010' ;Rx2 IORLW B'00000001' ;Rx1 IORLW B'00000000' ;Rx0 movwf INTPPS movwf T0CKIPPS movwf T1CKIPPS movwf T1GPPS movwf T3CKIPPS movwf T3GPPS movwf T5CKIPPS movwf T5GPPS movwf T2INPPS movwf T4INPPS movwf T6INPPS movwf CCP1PPS movwf CCP2PPS movwf CCP3PPS movwf CCP4PPS movwf SMT1WINPPS movwf SMT1SIGPPS movwf MDCARLPPS movwf MDCARHPPS movwf MDSRCPPS movwf CLCIN0PPS movwf CLCIN1PPS movwf CLCIN2PPS movwf CLCIN3PPS movwf ADACTPPS movwf SSP1CLKPPS movwf SSP1DATPPS movwf SSP1SSPPS movwf SSP2CLKPPS movwf SSP2DATPPS movwf SSP2SSPPS movwf RX1DTPPS movwf RX1PPS movwf RXPPS movwf CK1PPS movwf CKPPS movwf TX1CKPPS RETURN ;********************************************************************** SET_ADC2 ;-----Bank1------------------ movlb .1 movwf ADLTHH ;ADC Lower Threshold Register movwf ADLTHL movwf ADUTHH ;ADC Upper Threshold Register movwf ADUTHL movf ADERRH,W ;ADC Setpoint Error Register movf ADERRL,W movwf ADSTPTH ;ADC Threshold Setpoint Register movwf ADSTPTL movf ADFLTRH,W ;ADC Filter Register movf ADFLTRL,W movwf ADACCU ;ADC Accumulator Register 18bit 2/8/8 movwf ADACCH movwf ADACCL movwf ADCNT ;ADC Repeat Counter Register movwf ADRPT ;ADC Repeat Setting Register movf ADPREVH,W ;ADC Previous Result Register movf ADPREVL,W ;-----Bank2------------------ movlb .2 ADCON0,ADCONT ;1= GO is retriggered upon completion of each conversion trigger until TIF is set (if SOI is set) or until GO is cleared (regardless of the value of SOI) ;0 GO is cleared upon completion of each conversion trigger ADCON1,ADPPOL ;1 PRE>0 & ADC input is I/O pin Pin shorted to AVDD 0 PRE>0 & ADC input is I/O pin Pin shorted to VSS ;1 PRE>0 & ADC input is internal CHOLD Shorted to AVDD 0 PRE>0 & ADC input is internal CHOLD Shorted to VSS ADCON1,ADDSEN ;1 Two conversions are performed on each trigger. Data from the first conversion appears in PREV ;0 One conversion is performed for each trigger ADCON1,ADIPEN ;1 DSEN = 1 The precharge and guard signals in the second conversion cycle are the opposite polarity of the first cycle ;0 DSEN = 1 Both Conversion cycles use the precharge and guards specified by PPOL and GPOL ADCON1,ADGPOL ;1 ADC guard Ring outputs start as digital high during Precharge stage ;0 ADC guard Ring outputs start as digital low during Precharge stage ;ADCON1,ADGBOE ;ADCON1,ADGAOE movlw .20 ;Number of pF in the additional capacitance movwf ADCAP ;Additional Sample Capacitor Selection Register 5bit movlw .0 ;Number of ADC clocks in the precharge time movwf ADPREH ;ADC Precharge Time Control Register movwf ADPREL ; clrw ;MD[2:0] ADC Operating Mode Selection bits( ;IORLW B'00000100' ;Low-pass Filter mode ;IORLW B'00000011' ;Burst Average mode ;IORLW B'00000010' ;Average mode ;IORLW B'00000001' ;Accumulate mode ;IORLW B'00000000' ;Basic (Legacy) mode ;6:4 ADC Accumulated Calculation Right Shift Select bits ;IORLW B'01010000' ;MD = b'100' Low-pass filter time constant is 2CRS, filter gain is 1:1 movwf ADCON2 ;MD = b'011' to b'001' The accumulated value is right-shifted by CRS (divided by 2CRS)(1,2) BCF ADCON2,ADPSIS ;1 FLTR is transferred to PREV at start-of-conversion 0 ADRES is transferred to PREV at start-of-conversion BCF ADCON2,ADACLR ;1= ACC, OV and CNT bits are cleared 0= Clearing action is complete (or not started) ;;ADC Error Calculation Mode clrw ;DSEN = 0 Single-Sample DSEN = 1 CVD Double-Sample ;IORLW B'00000000' ;ADRES-ADPREV ADRES-ADPREV First derivative of single measurement(2) Actual CVD result in CVD mode(2) ;IORLW B'00010000' ;ADRES-ADSTPT (ADRES-ADPREV)-ADSTPT Actual result vs. setpoint ;IORLW B'00100000' ;ADRES-ADFLTR (ADRES-ADPREV)-ADFLTR Actual result vs. averaged/filtered value ;IORLW B'01000000' ;ADPREV-ADFLTR ADPREV-ADFLTR First derivative of filtered value(3) (negative) ;IORLW B'01010000' ;ADLFTR-ADSTPT ADFLTR-ADSTPT Average/filtered value vs. setpoint ;IORLW B'00000111' ;Interrupt regardless of threshold test results ;IORLW B'00000110' ;Interrupt if ERR>UTH ;IORLW B'00000101' ;Interrupt if ERR≤UTH ;IORLW B'00000100' ;Interrupt if ERRUTH ;IORLW B'00000011' ;Interrupt if ERR>LTH and ERR SSPOV = 1, and the SSP1BUF is not updated BCF SSP1STAT,SMP ;1= Input data sampled at end of data output time 0= Input data sampled at middle of data output time BSF SSP1STAT,CKE ;1= Transmit occurs on transition from active to Idle clock state 0= Transmit occurs on transition from Idle to active clock state BCF SSP1CON1,CKP ;1= Idle state for SCK is a high level 0= Idle state for SCK is a low level BCF SSP1CON1,SSPM3 ;0000= SPI Master mode, clock = Fosc/4 BCF SSP1CON1,SSPM2 ;0001= SPI Master mode, clock = Fosc/16 BSF SSP1CON1,SSPM1 ;0010= SPI Master mode, clock = Fosc/64 32MHz => SCK = 500KHz BCF SSP1CON1,SSPM0 ;0011= SPI Master mode, clock = TMR2 output/2 ;1010= SPI Master mode, clock = FOSC/(4 * (SSPxADD+1)) ;0100= SPI Slave mode, clock = SCKx pin, SSx pin control enabled ;0101= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin BSF SSP1CON1,SSPEN ;1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins 0 = Disables, I/O port movlb .0 RETURN ; ;SET_SPI2 ;Настройка на SPI1 модула ;BCF TRISB,7 ;SCK2 0=Master/1=Slave ;BCF TRISB,5 ;SDI2 ;BCF TRISC,1 ;SDO2 ;BCF TRISC,0 ;SS2 0=Master/1=Slave ;RETURN ; SET_ZCD movlb .18 BCF ZCDCON,ZCDINTN ;EQU H'0000' BCF ZCDCON,ZCDINTP ;EQU H'0001' BCF ZCDCON,ZCDPOL ;EQU H'0004' BCF ZCDCON,ZCDOUT ;EQU H'0005' BCF ZCDCON,ZCDSEN ;EQU H'0007' movlb .0 RETURN ; SET_DAC movlb .18 ;FVR buffer VREF+ AVDD DAC Positive Source Select bit BCF DAC1CON0,DAC1PSS1 ;1 0 0 BCF DAC1CON0,DAC1PSS0 ;0 1 0 BCF DAC1CON0,DAC1NSS ;1 VREF- 0 AVSS BCF DAC1CON0,DAC1OE1 ;1= DAC voltage level is output on the DAC1OUT1 pin 0= DAC voltage level is disconnected from the DAC1OUT1 pin BSF DAC1CON0,DAC1EN ;1= DAC is enabled 0= DAC is disabled movlw 0x00 ;4:0 movwf DAC1CON1 ;DAC Data Register movlb .0 RETURN ;;;; ORG 0x1020 ;Page2 DW 0x0000 ;14bit