;LZ4GV 2021- Firmware EQU .1 list P=10f322 ; list directive to define processor #include ; processor specific variable definitions ;Set Configuration Register __CONFIG _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _BOREN_ON & _LVP_OFF & _LPBOR_OFF & _BORV_HI & _WRT_OFF ;_BORV_HI = 2.70V ; _FOSC_EC _WDTE_ON _PWRTE_OFF _MCLRE_ON _CP_ON _BOREN_OFF _LVP_ON _LPBOR_ON _BORV_LO _WRT_BOOT ;_BORV_LO = 2.40V ; _WDTE_NSLEEP _BOREN_NSLEEP _WRT_HALF ; _WDTE_SWDTEN _BOREN_SBODEN _WRT_ALL OSCTUNE_MNL EQU .0 ;Central frequency min .32 - .63 0 .1 - .31 max #define PORTA0 PORTA,RA0 ;Pin 1 #define PORTA1 PORTA,RA1 ;Pin 3 #define PORTA2 PORTA,RA2 ;Pin 4 #define PORTA3 PORTA,RA3 ;Pin 6 Input #define PORTA0IO TRISA,TRISA0 #define PORTA1IO TRISA,TRISA1 #define PORTA2IO TRISA,TRISA2 ;0x40 to 0x7F Bank 0 #define STATBIT 0x40,0 ; ;TMR0MEM EQU 0x74 ; ;TMR1LMEM EQU 0x75 ; ;TMR1HMEM EQU 0x76 ; ;FSRMEM EQU 0x77 ; ;PCLMEM EQU 0x78 ; ACQT EQU 0x79 ;ADC RADRESH EQU 0x7B ;ADC REEADR EQU 0x7C ;EEPROM REEDATA EQU 0x7D ;EEPROM OPTIONMEM EQU 0x7E ; INTCONMEM EQU 0x7F ; #define Bank0_1 BSR,0 ;0= Bank0 1= Bank1 INDF EQU INDF0 FSR EQU FSR0L ORG 0xF000 ;Initialize EEPROM locations 0xF000 - 0xF0FF DE 0x00,0x01,0x02,0x03 ORG 0x0000 GOTO START ;********************************************************************** ORG 0x0004 ;Interrupt vector location clrf PCLATH ;0- Work. Page0 ;Page 83 btfsc INTCON,IOCIF ;PORTA Change Interrupt Global Flag GOTO INT_PORTCHANGE ;--> btfsc INTCON,TMR0IF ;Overflow TMR0 GOTO INT_TMR0 ;--> btfsc INTCON,INTF GOTO INT_EXTINT ;--> GOTO INT_END ;--> ;---------------------------------------------------------------------- ; USER INTERRUPT SERVICE ROUTINE GOES HERE ;---------------------------------------------------------------------- INT_PORTCHANGE CLRF IOCAF ;PORTA Flag Register Interrupt-On-Change MOVLW 0xFF XORWF IOCAF,W ANDWF IOCAF,F bcf INTCON,IOCIF ;PORTA Change Interrupt Global Flag GOTO INT_END ;--> INT_TMR0 bcf INTCON,TMR0IF ;TMR0 Overflow Interrupt Flag GOTO INT_END ;--> INT_EXTINT bcf INTCON,INTF ;RA2/INT Change Interrupt Flag GOTO INT_END ;--> ; INT_END ;Automatically handles context restoration for W, STATUS, BSR, FSR, and PCLATH RETFIE ;Return From Interrupt / Enable Global Interrupts ;********************************************************************** BEGIN movlw 0x40 ;Start Address RAM. movwf FSR CLRRAM clrf INDF movlw 0x7F ;End Address RAM. subwf FSR,W incf FSR,F ; btfss STATUS,C ;FSR = or > W C=1 GOTO CLRRAM ;FSR < W C=0 ;********** Начало *********** MAIN ;********************************************************************** ; MAIN PROGRAM ;********************************************************************** GOTO MAIN ;********** Край ************* ;********************************************************************** MOVLW .4 ; MOVWF TMR0 ; BCF INTCON,TMR0IF ;Overflow TMR0 MOVLW 0x0B ; MOVWF TMR2 ; BCF PIR1,TMR2IF ;Overflow TMR2 MOVLW 0x80 ;Pulse Width Modulation 1 CLRF PWM1DCH ;Bit 9 - 2 BCF PWM1DCL,PWM1DCL1 ;Bit 1 BCF PWM1DCL,PWM1DCL0 ;Bit 0 ; MOVLW .100 ; ; SUBWF RADRESH,W ;ADRESH > W C=1 ; BTFSC STATUS,C ;ADRESH = W C=1 ; GOTO ;ADRESH < W C=0 ; GOTO ; ; movlw .50 ; sublw .20 ;W < .20 C=1 ; BTFSC STATUS,C ;W = .20 C=1 ; GOTO ;W > .20 C=0 ; GOTO ; ; MOVF OPTION_REG,W ;Запомня състоянието на OPTION_REG. MOVWF OPTIONMEM ;Променя TMR0 ANDLW B'11111000' ;Нулира само PS2 PS1 PS0 IORLW B'00000001' ;Променя Fosc/4/4 = 4uS MOVWF OPTION_REG ; MOVF OPTIONMEM,W ; MOVWF OPTION_REG ; ; ;CALL READE ;In:F(REEADR) Out:F(REEDATA),W ;CALL WRITE ;In:F(REEADR,REEDATA) 14bit Data movlw RA0_AN0 ; movlw RA1_AN1 movlw RA2_AN2 CALL READ_ADC ;In: W(Analog Select) Out:F(RADRESH) ;******* BCF INTCON,GIE ;Disable All INTs. BTFSC INTCON,GIE ;See AN576 GOTO $-2 ; BSF INTCON,GIE ;Enable All INTs. ;******* GOTO MAIN ;********************************************************************** ;********************************************************************** WRITE ;Page 50 ;In:F(REEADR,REEDATA) 14bit Data BSF PMADRH,PMADR8 ;Bit 8 MOVF REEADR,W MOVWF PMADRL ;Bit 7 - 0 CLRF PMDATH MOVF REEDATA,W MOVWF PMDATL BCF PMCON1,CFGS ;0= Access Flash program memory BCF PMCON1,FREE ;0= Performs an write operation on the next WR command ;BCF PMCON1,LWLO ;? BCF INTCONMEM,GIE ; BTFSC INTCON,GIE ;Запазва състоянието. BSF INTCONMEM,GIE ; BCF INTCON,GIE ;Disable INTs. BTFSC INTCON,GIE ;See AN576 GOTO $-2 ; BSF PMCON1,WREN ;1= Allows write cycles 0= MOVLW 0x55 ; MOVWF PMCON2 ; MOVLW 0xAA ; MOVWF PMCON2 ; BSF PMCON1,WR ; BTFSC PMCON1,WR ;1= Write Cycles 0= Write cycles to the EEPROM is complete GOTO $-1 ;-^ ;BTFSC PMCON1,WRERR ;1= Write Terminated 0= Write Operation Completed ;NOP BCF PMCON1,WREN ;disable write BTFSC INTCONMEM,GIE ; BSF INTCON,GIE ; RETURN ; READE ;In:F(REEADR) Out:F(REEDATA),W BSF PMADRH,PMADR8 ;Bit 8 MOVF REEADR,W MOVWF PMADRL ;Bit 7 - 0 BCF PMCON1,CFGS BSF PMCON1,RD ;1 - initiates an EEPOM read BTFSC PMCON1,RD ;rd done? GOTO $-1 ;no then loop MOVF PMDATL,W MOVWF REEDATA RETURN ; ; RA0_AN0 EQU B'00000000' ;Analog Channel Select bits <4:2> RA1_AN1 EQU B'00000100' RA2_AN2 EQU B'00001000' INT_TEMPER EQU B'00011000' ;Temperature Indicator FVR_MODULE EQU B'00011100' ;FVR Module READ_ADC ;Page 88 ;8bit Analog-to-Digital Converter In: W(Analog Select) Out:F(RADRESH) MOVWF ADCON ;Analog Channel Select bits <4:2> BSF ADCON,ADON ;1= A/D Converter Module Enable 0= Disable ;MOVLW .10 ;Fosc=16MHz ;MOVLW .5 ;Fosc= 8MHz MOVLW .2 ;Fosc= 4MHz MOVWF ACQT ;Min Acquisition Time 5uS DECFSZ ACQT,F ;- GOTO $-1 ;-^ BSF ADCON,GO_NOT_DONE ;Start Convertion BTFSC ADCON,GO_NOT_DONE ; GOTO $-1 ;-^ BCF ADCON,ADON ;0 = A/D converter is shut_off MOVF ADRES,W MOVWF RADRESH RETURN ; ; SET_ADC ;Page 88 ;16MHz 16MHz* 16MHz* 16MHz 8MHz 4MHz 1MHz Select A/D Conversion Clock. ;FRC Fosc/64 Fosc/32 Fosc/16 Fosc/8 Fosc/4 Fosc/2 BCF ADCON,ADCS2 ;x 1 0 1 0 1 0 BCF ADCON,ADCS1 ;1 1 1 0 0 0 0 BSF ADCON,ADCS0 ;1 0 0 1 1 0 0 RETURN ; SET_FVR ;Page 77 ;Fixed Voltage Reference. Fixed Voltage Reference output cannot exceed VDD ;For ADC BCF FVRCON,ADFVR1 ;1= 4.096V 1= 2.048V 0= 1.024V 0= is OFF BCF FVRCON,ADFVR0 ;1= 0= 1= 0= BSF FVRCON,FVREN ;1= FVR Enable ;BTFSS FVRCON,FVRRDY ;1 = Fixed Voltage Reference otput is ready for use ;NOP RETURN ; SET_PWM1 ;Page 100 ;Pulse Width Modulation RA0 Use TMR2 MOVLW 0xFF ; MOVWF PR2 ;Page BCF T2CON,T2CKPS1 ;Timer prescaler 1= /64 1= /16 0= /4 0= /1 BCF T2CON,T2CKPS0 ;Timer prescaler 1 0 1 0 BSF T2CON,TMR2ON ;1=Enables Timer2 0=Stop Timer2 CLRF PWM1DCH ;Bit 9 - 2 BCF PWM1DCL,PWM1DCL1 ;Bit 1 BCF PWM1DCL,PWM1DCL0 ;Bit 0 CLRF TMR2 ; BCF PIR1,TMR2IF ; BTFSS PIR1,TMR2IF ;New PWM cycle? GOTO $-1 ; BCF TRISA,0 BCF PWM1CON,PWM1POL ;1= PWM output is active-low 0= PWM output is active-high BSF PWM1CON,PWM1OE ;1= Output to PWMx pin is enabled 0= Output to PWMx pin is disabled BSF PWM1CON,PWM1EN ;1= PWM module is enabled 0= PWM module is disabled ;btfss PWM1CON,PWM1OUT ;PWM Module Output Value bit RETURN ; SET_PWM2 ;Page 100 ;Pulse Width Modulation RA1 Use TMR2 MOVLW 0xFF ; MOVWF PR2 ;Page BCF T2CON,T2CKPS1 ;Timer prescaler 1= /64 1= /16 0= /4 0= /1 BCF T2CON,T2CKPS0 ;Timer prescaler 1 0 1 0 BSF T2CON,TMR2ON ;1=Enables Timer2 0=Stop Timer2 CLRF PWM2DCH ;Bit 9 - 2 BCF PWM2DCL,PWM2DCL1 ;Bit 1 BCF PWM2DCL,PWM2DCL0 ;Bit 0 CLRF TMR2 ; BCF PIR1,TMR2IF ; BTFSS PIR1,TMR2IF ;New PWM cycle? GOTO $-1 ; BCF TRISA,1 BCF PWM2CON,PWM2POL ;1= PWM output is active-low 0= PWM output is active-high BSF PWM2CON,PWM2OE ;1= Output to PWMx pin is enabled 0= Output to PWMx pin is disabled BSF PWM2CON,PWM2EN ;1= PWM module is enabled 0= PWM module is disabled ;btfss PWM2CON,PWM2OUT ;PWM Module Output Value bit RETURN ; SET_TMR0 ;Page 95 8Bit BCF OPTION_REG,T0CS ;1=T0CKI pin 0=Intrnal Clock Source Fosc/4 ;BTFSC OPTION_REG,T0CS ; ;BCF OPTION_REG,T0SE ;1= High -> Low T0CKI 0= Low -> High T0CKI BCF OPTION_REG,PSA ;0 - Prescaler Is Assigned To The TMR0 Module ;BTFSC OPTION_REG,PSA ;1 = Prescaler is not assigned to the Timer0 module ;RETURN ;--> MOVF OPTION_REG,W ; ANDLW B'11111000' ;Нулира само PS2 PS1 PS0 ;IORLW B'00000000' ;Fosc/4/2 4MHz => 2uS ;IORLW B'00000001' ;Fosc/4/4 ;IORLW B'00000010' ;Fosc/4/8 ;IORLW B'00000011' ;Fosc/4/16 ;IORLW B'00000100' ;Fosc/4/32 ;IORLW B'00000101' ;Fosc/4/64 ;IORLW B'00000110' ;Fosc/4/128 IORLW B'00000111' ;Fosc/4/256 4MHz => 256uS MOVWF OPTION_REG ; RETURN ;--> ; SET_TMR2 ;Page 96 8Bit ;Timer1 Module: Max period 16S (Fosc/4) 4MHz000 BSF T2CON,T2CKPS1 ;Timer prescaler 1= /64 1= /16 0= /4 0= /1 BCF T2CON,T2CKPS0 ;Timer prescaler 1 0 1 0 ;BSF T2CON,TOUTPS3 ;Timer2 Output Postscaler Select bits, Sets Flag Bit TMR2IF ;BSF T2CON,TOUTPS2 ; ;BSF T2CON,TOUTPS1 ; ;BSF T2CON,TOUTPS0 ; BSF T2CON,TMR2ON ;1=Enables Timer2 0=Stop Timer2 RETURN ; SET_WDT ;Page 48 1mS to 256S WDT time is based on 31 kHz LFINTOSC MOVLW B'00010110' ;Interval 2S 1:65536 ;MOVLW B'00100100' ;Interval 256S MOVWF WDTCON ; BSF WDTCON,SWDTEN ;1=WDT Is Turned ON If Configuration 2007h Enable 0=WDT Is Turned OFF RETURN ; SET_INT_PORTCHANGE ;Page MOVLW B'00000000' ;x x x x IOCAP3 IOCAP2 IOCAP1 IOCAP0 MOVWF IOCAP ;1=Interrupt-on-change Positive Enabled 0=Interrupt-on-change Positive Disabled MOVLW B'00000000' ;x x x x IOCAN3 IOCAN2 IOCAN1 IOCAN0 MOVWF IOCAN ;1=Interrupt-on-change Negative Enabled 0=Interrupt-on-change Negative Disabled CLRF IOCAF ;PORTA Flag Register bcf INTCON,IOCIF ;PORTA Change Interrupt Global Flag bsf INTCON,IOCIE ;1=PORTA Change Interrupt Enables 0=PORTA Change Interrupt Disable RETURN SET_INT_EXTINT ;Page Pin RA2 BSF OPTION_REG,INTEDG;1=Rising RA2/INT Interrupt 0=Falling RA2/INT Interrupt BCF INTCON,INTF ;RA2/INT Change Interrupt Flag BSF INTCON,INTE ;1=RA2/INT Change Interrupt Enables 0=RA2/INT Change Interrupt Disable RETURN SET_INT_TMR0 BSF INTCON,TMR0IE ;1=Enables TMR0 Overflow Interrupt 0=Disables TMR0 Overflow Interrupt BCF INTCON,TMR0IF ;TMR0 Overflow Interrupt Flag RETURN ; SET_OSC ;Page 24 ;16MHz 8MHz 4MHz 2MHz 1MHz 500KHz 250KHz 31KHz ExtOSC BSF OSCCON,IRCF2 ;1 1 1 1 0 0 0 0 Cofig.W. BCF OSCCON,IRCF1 ;1 1 0 0 1 1 0 0 BSF OSCCON,IRCF0 ;1 0 1 0 1 0 1 0 ;btfss OSCCON,HFIOFR ;1= 16MHz Internal Oscillator is Ready ;btfss OSCCON,LFIOFR ;1= 31kHz Internal Oscillator is Ready ;btfss OSCCON,HFIOFS ;1= 16MHz Internal Oscillator is Stabile BCF CLKRCON,CLKROE ;1= Reference Clock Output Enable RA2 RETURN ; SET_IO ;Page 68 CLRF LATA ;Page MOVLW B'00000000' ;X X X X X RA2 RA1 RA0 MOVWF ANSELA ;1= Analog Input 0= Digital I/O MOVLW B'00000000' ;X X X X RA3 RA2 RA1 RA0 MOVWF WPUA ;1=Pull-up Enable 0=Pull-up Disabled BSF OPTION_REG,NOT_WPUEN ;1=Pull-up Global Disabled 0=Pull-up Global Enable MOVLW B'00001111' ;1=Input 0=Output MOVWF TRISA ;X X X 1 RA2 RA1 RA0 RETURN ;********************************************************************** ;*******Първоначална настройка на микроконтролера********************** START clrf PORTA clrf INTCON ;Забранява всички прекъсвания. ;clrf PIE1 ;Voltage Regulator Power Mode Selection bit BCF VREGCON,VREGPM1 ;1= Power-Save Sleep mode enabled in Sleep. Draws lowest current in Sleep, slower wake-up ;0= Low-Power mode enabled in Sleep. Draws higher current in Sleep, faster wake-up CALL SET_OSC ;Oscillator configuration !!! CALL SET_IO ;Настройка на портовете In, Out, Analog, Pull-up ;CALL SET_TMR0 ;Настройка на Timer0 ;CALL SET_TMR2 ;Настройка на Timer2 ;CALL SET_WDT ; ;CALL SET_ADC ;8bit Vref+=Vdd ;CALL SET_FVR ; ;CALL SET_PWM1 ;Page 100 ;Pulse Width Modulation RA0 Use TMR2 ;CALL SET_PWM2 ;Page 100 ;Pulse Width Modulation RA1 Use TMR2 ;CALL SET_CWG ;??? Complementary Waveform Generator ;CALL SET_NCO ;??? Numerically Controlled Oscillator ;CALL SET_CLC ;??? Configurable Logic Cell ;CALL SET_INT_PORTCHANGE ;CALL SET_INT_EXTINT ;CALL SET_INT_TMR0 ;BSF INTCON,GIE ;1=Enables All Interrupts 0=Disables All Interrupts GOTO BEGIN ;--^ ;********************************************************************** END ;0x01FF ;********************************************************************** ;********************************************************************** ;********************************************************************** ; Temperature Indicator ; BCF FVRCON,TSRNG ; BCF FVRCON,TSEN ;;;; SET_NCO movlb .9 ;Page 225 ;NCO1ACCL ;NCO1ACCH ;NCO1ACCU CLRW ;765 Pulse Frequency mode IORLW b'11100000' ;111 = NCO1 output is active for 128 input clock periods ;IORLW b'11000000' ;110 = NCO1 output is active for 64 input clock periods ;IORLW b'10100000' ;101 = NCO1 output is active for 32 input clock periods ;IORLW b'10000000' ;100 = NCO1 output is active for 16 input clock periods ;IORLW b'01100000' ;011 = NCO1 output is active for 8 input clock periods ;IORLW b'01000000' ;010 = NCO1 output is active for 4 input clock periods ;IORLW b'00100000' ;001 = NCO1 output is active for 2 input clock periods ;IORLW b'00000000' ;000 = NCO1 output is active for 1 input clock period ;10 IORLW b'00000000' ;00 = HFINTOSC (16 MHz) ;IORLW b'00000000' ;01 = FOSC ;IORLW b'00000000' ;10 = CLC1OUT MOVWF NCO1CLK BCF NCO1CON,N1PFM ;1 = NCO1 operates in Pulse Frequency mode 0 = NCO1 operates in Fixed Duty Cycle mode, divide by 2 BCF NCO1CON,N1POL ;1 = NCO1 output signal is inverted 0 = NCO1 output signal is not inverted ; NCO1CON,N1OUT ;Read Only Output bit BSF NCO1CON,N1EN ;1 = NCO1 module is enable 0 = NCO1 module is disabled ;clrf NCO1INCU ;Foverflow = Fosc * NCO1INC / 1048576 ;clrf NCO1INCH ;NCO1INC = Fout / 30.5 Fosc=32MHz Pulse mode x 31,25 ns ;movlw 0x01 ;NCO1INC = Fout / 15,26 Fosc=32MHz PWM=50% Fixed Duty ;movwf NCO1INCL movlb .29 ;Page144 movlw b'00011101' ;NCO1 -> RA4 pin3 movwf RA4PPS movlb .1 ; bcf TRISA,TRISA4 ;Output! movlb .0 ; RETURN ;;; NCO1ACC EQU H'0027' NCO1ACCL EQU H'0027' NCO1ACCH EQU H'0028' NCO1ACCU EQU H'0029' NCO1INC EQU H'002A' NCO1INCL EQU H'002A' NCO1INCH EQU H'002B' NCO1INCU EQU H'002C' NCO1CON EQU H'002D' NCO1CLK EQU H'002E' ;----- NCO1ACCL Bits ----------------------------------------------------- NCO1ACC0 EQU H'0000' NCO1ACC1 EQU H'0001' NCO1ACC2 EQU H'0002' NCO1ACC3 EQU H'0003' NCO1ACC4 EQU H'0004' NCO1ACC5 EQU H'0005' NCO1ACC6 EQU H'0006' NCO1ACC7 EQU H'0007' ;----- NCO1ACCH Bits ----------------------------------------------------- NCO1ACC8 EQU H'0000' NCO1ACC9 EQU H'0001' NCO1ACC10 EQU H'0002' NCO1ACC11 EQU H'0003' NCO1ACC12 EQU H'0004' NCO1ACC13 EQU H'0005' NCO1ACC14 EQU H'0006' NCO1ACC15 EQU H'0007' ;----- NCO1ACCU Bits ----------------------------------------------------- NCO1ACC16 EQU H'0000' NCO1ACC17 EQU H'0001' NCO1ACC18 EQU H'0002' NCO1ACC19 EQU H'0003' ;----- NCO1INCL Bits ----------------------------------------------------- NCO1INC0 EQU H'0000' NCO1INC1 EQU H'0001' NCO1INC2 EQU H'0002' NCO1INC3 EQU H'0003' NCO1INC4 EQU H'0004' NCO1INC5 EQU H'0005' NCO1INC6 EQU H'0006' NCO1INC7 EQU H'0007' ;----- NCO1INCH Bits ----------------------------------------------------- NCO1INC8 EQU H'0000' NCO1INC9 EQU H'0001' NCO1INC10 EQU H'0002' NCO1INC11 EQU H'0003' NCO1INC12 EQU H'0004' NCO1INC13 EQU H'0005' NCO1INC14 EQU H'0006' NCO1INC15 EQU H'0007' ;----- NCO1CON Bits ----------------------------------------------------- N1PFM EQU H'0000' N1POL EQU H'0004' N1OUT EQU H'0005' N1OE EQU H'0006' N1EN EQU H'0007' ;----- NCO1CLK Bits ----------------------------------------------------- N1CKS0 EQU H'0000' N1CKS1 EQU H'0001' N1PWS0 EQU H'0005' N1PWS1 EQU H'0006' N1PWS2 EQU H'0007' ;;; SET_CWG ;Page 129 ;Complementary Waveform Generator CWG1CON0 EQU H'0039' CWG1CON1 EQU H'003A' CWG1CON2 EQU H'003B' CWG1DBR EQU H'003C' CWG1DBF EQU H'003D' ;----- CWG1CON0 Bits ----------------------------------------------------- G1CS0 EQU H'0000' G1POLA EQU H'0003' G1POLB EQU H'0004' G1OEA EQU H'0005' G1OEB EQU H'0006' G1EN EQU H'0007' ;----- CWG1CON1 Bits ----------------------------------------------------- G1IS0 EQU H'0000' G1IS1 EQU H'0001' G1ASDLA0 EQU H'0004' G1ASDLA1 EQU H'0005' G1ASDLB0 EQU H'0006' G1ASDLB1 EQU H'0007' ;----- CWG1CON2 Bits ----------------------------------------------------- G1ASDSFLT EQU H'0000' G1ASDSCLC1 EQU H'0001' G1ARSEN EQU H'0006' G1ASE EQU H'0007' ;----- CWG1DBR Bits ----------------------------------------------------- CWG1DBR0 EQU H'0000' CWG1DBR1 EQU H'0001' CWG1DBR2 EQU H'0002' CWG1DBR3 EQU H'0003' CWG1DBR4 EQU H'0004' CWG1DBR5 EQU H'0005' ;----- CWG1DBF Bits ----------------------------------------------------- CWG1DBF0 EQU H'0000' CWG1DBF1 EQU H'0001' CWG1DBF2 EQU H'0002' CWG1DBF3 EQU H'0003' CWG1DBF4 EQU H'0004' CWG1DBF5 EQU H'0005' ;;;; SET_CLC ;Page 104 ;Configurable Logic Cell CLC1CON EQU H'0031' CLC1SEL0 EQU H'0032' CLC1SEL1 EQU H'0033' CLC1POL EQU H'0034' CLC1GLS0 EQU H'0035' CLC1GLS1 EQU H'0036' CLC1GLS2 EQU H'0037' CLC1GLS3 EQU H'0038' ;----- CLC1CON Bits ----------------------------------------------------- LC1MODE0 EQU H'0000' LC1MODE1 EQU H'0001' LC1MODE2 EQU H'0002' LC1INTN EQU H'0003' LC1INTP EQU H'0004' LC1OUT EQU H'0005' LC1OE EQU H'0006' LC1EN EQU H'0007' LCMODE0 EQU H'0000' LCMODE1 EQU H'0001' LCMODE2 EQU H'0002' LCINTN EQU H'0003' LCINTP EQU H'0004' LCOUT EQU H'0005' LCOE EQU H'0006' LCEN EQU H'0007' ;----- CLC1SEL0 Bits ----------------------------------------------------- LC1D1S0 EQU H'0000' LC1D1S1 EQU H'0001' LC1D1S2 EQU H'0002' LC1D2S0 EQU H'0004' LC1D2S1 EQU H'0005' LC1D2S2 EQU H'0006' D1S0 EQU H'0000' D1S1 EQU H'0001' D1S2 EQU H'0002' D2S0 EQU H'0004' D2S1 EQU H'0005' D2S2 EQU H'0006' ;----- CLC1SEL1 Bits ----------------------------------------------------- LC1D3S0 EQU H'0000' LC1D3S1 EQU H'0001' LC1D3S2 EQU H'0002' LC1D4S0 EQU H'0004' LC1D4S1 EQU H'0005' LC1D4S2 EQU H'0006' D3S0 EQU H'0000' D3S1 EQU H'0001' D3S2 EQU H'0002' D4S0 EQU H'0004' D4S1 EQU H'0005' D4S2 EQU H'0006' ;----- CLC1POL Bits ----------------------------------------------------- LC1G1POL EQU H'0000' LC1G2POL EQU H'0001' LC1G3POL EQU H'0002' LC1G4POL EQU H'0003' LC1POL EQU H'0007' G1POL EQU H'0000' G2POL EQU H'0001' G3POL EQU H'0002' G4POL EQU H'0003' POL EQU H'0007' ;----- CLC1GLS0 Bits ----------------------------------------------------- LC1G1D1N EQU H'0000' LC1G1D1T EQU H'0001' LC1G1D2N EQU H'0002' LC1G1D2T EQU H'0003' LC1G1D3N EQU H'0004' LC1G1D3T EQU H'0005' LC1G1D4N EQU H'0006' LC1G1D4T EQU H'0007' D1N EQU H'0000' D1T EQU H'0001' D2N EQU H'0002' D2T EQU H'0003' D3N EQU H'0004' D3T EQU H'0005' D4N EQU H'0006' D4T EQU H'0007' ;----- CLC1GLS1 Bits ----------------------------------------------------- LC1G2D1N EQU H'0000' LC1G2D1T EQU H'0001' LC1G2D2N EQU H'0002' LC1G2D2T EQU H'0003' LC1G2D3N EQU H'0004' LC1G2D3T EQU H'0005' LC1G2D4N EQU H'0006' LC1G2D4T EQU H'0007' D1N EQU H'0000' D1T EQU H'0001' D2N EQU H'0002' D2T EQU H'0003' D3N EQU H'0004' D3T EQU H'0005' D4N EQU H'0006' D4T EQU H'0007' ;----- CLC1GLS2 Bits ----------------------------------------------------- LC1G3D1N EQU H'0000' LC1G3D1T EQU H'0001' LC1G3D2N EQU H'0002' LC1G3D2T EQU H'0003' LC1G3D3N EQU H'0004' LC1G3D3T EQU H'0005' LC1G3D4N EQU H'0006' LC1G3D4T EQU H'0007' D1N EQU H'0000' D1T EQU H'0001' D2N EQU H'0002' D2T EQU H'0003' D3N EQU H'0004' D3T EQU H'0005' D4N EQU H'0006' D4T EQU H'0007' ;----- CLC1GLS3 Bits ----------------------------------------------------- LC1G4D1N EQU H'0000' LC1G4D1T EQU H'0001' LC1G4D2N EQU H'0002' LC1G4D2T EQU H'0003' LC1G4D3N EQU H'0004' LC1G4D3T EQU H'0005' LC1G4D4N EQU H'0006' LC1G4D4T EQU H'0007' G4D1N EQU H'0000' G4D1T EQU H'0001' G4D2N EQU H'0002' G4D2T EQU H'0003' G4D3N EQU H'0004' G4D3T EQU H'0005' G4D4N EQU H'0006' G4D4T EQU H'0007' ;;;;;;;;;;;;;;;;; ; BORCON,BORRDY ; BORCON,BORFS ; BORCON,SBOREN ; PCON,NOT_BOR ; PCON,NOT_POR